
## input file for OSCI TLM 2.0 lt_mixed_endian example
#
#  copyright OSCI 2009
#
#  no attempt yet to play with non-aligned accesses
#
#  syntax
#   'l' for load, 's' for store, 'w' for "switch CPU" at very beginning of line
#   '8', '16' or '32' directly following the 'l' or 's' to indicate data type
#   hex value for address after at least one space
#   for load, hex value for number of data words after at least one space
#   for store, hex value for each data word, space-separated
##

# starts in BE CPU
# store some bytes and read them back
s8 0   0 1 2 3 4 5 6 7
l8 0   8
l8 1   7
l8 5   3

# read them back as halfwords
l16 0   4
l16 2   3
l16 4   1

# read them back as words
l32 0   2
l32 4   1

# switch to LE CPU and do the same thing
w
s8 0   0 1 2 3 4 5 6 7
l8 0   8
l8 1   7
l8 5   3
l16 0   4
l16 2   3
l16 4   1
l32 0   2
l32 4   1

# switch back to BE CPU and read the data stored by the LE CPU to see how it is corrupted
w
l8 0   8
l8 1   7
l8 5   3
l16 0   4
l16 2   3
l32 0   2
l32 4   1

# sharing 32-bit data works fine
s32 20 13579bdf
w
l32 20   1

# sharing 16-bit data needs address mod
# first clear entire 32-bit word
s32 30   00000000
s16 30   ea62
w
l16 30   1
l16 32   1

# sharing 8-bit data needs address mod
s8 42   5a
w
l8 42   1
l8 41   1



